1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor device having a Chip-On-Chip structure in which a semiconductor chip is bonded onto another semiconductor chip.
2. Description of Related Art
One form of so-called a multi-chip type semiconductor device has a Chip-On-Chip structure in which a plurality of semiconductor chips are stacked. In a semiconductor device having a Chip-On-Chip structure, a sub-chip smaller than a main chip is bonded onto a surface of the main chip connected to outside. In some cases, a plurality of sub-chips are bonded onto a main chip.
Each of the main chip and the sub-chip has a plurality of metal bumps on its active surface provided with functional elements and wirings thereon. These metal bumps are mainly formed of a high melting point metal such as gold (Au), and a layer of a low melting point metal such as tin (Sn) is formed on each of the top portions of both or either of metal bumps of the main chip and the metal bumps of the sub-chip.
In a first conventional method for manufacturing a semiconductor device having a Chip-On-Chip structure, the active surface of the main chip and the active surface of the sub-chip are opposed to each other and the main chip and the sub-chip are heated to a temperature higher than the melting point (solidus temperature) of the low melting point metal. Thereby, the low melting point metal layers formed on the top portions of the metal bumps melt. Thereafter, the metal bumps of the main chip and the metal bumps of the sub-chip are positioned with respect to each other and brought close to (into contact with) each other, and the main chip and the sub-chip are cooled to a temperature lower than the melting point of the low melting point metal. As a result, the low melting point metal solidifies, and the metal bumps of the main chip and the metal bumps of the sub-chip are electrically and mechanically bonded together through the low melting point metal.
In a second conventional method for manufacturing a semiconductor device having a Chip-On-Chip structure, a load is applied on the main chip and the sub-chip so that the metal bumps of the main chip and the metal bumps of the sub-chip can be pressed against each other, and then the main chip and the sub-chip are heated to a temperature higher than the melting point (solidus temperature) of the low melting point metal. Thereby, the low melting point metal layers formed on the top portions of the metal bumps respectively melt. Thereafter, the main chip and the sub-chip are cooled to a temperature lower than the melting point of the low melting point metal. As a result, the low melting point metal solidifies, and the metal bumps of the main chip and the metal bumps of the sub-chip are electrically and mechanically bonded together through the low melting point metal.
In this case, if oxide films are formed on the surfaces of the metal bumps of the main chips and the metal bumps of the sub-chips, the oxide films are broken by pressing the metal bumps of the main chip and the metal bumps of the sub-chips against each other, so that the metal bumps of the main chip and the metal bumps of the sub-chip can be suitably bonded through the low melting point metal.
The abovementioned bonding may be carried out with the use of, instead of the main chip, a wafer before main chips are cut out therefrom. In this case, after the semiconductor wafer and the sub-chips are bonded together, the semiconductor wafer is cut into pieces of semiconductor chips each having a Chip-On-Chip structure.
However, in the abovementioned first manufacturing method, when the metal bumps of the main chip and the metal bumps of the sub-chips are brought close to each other, the molten low melting point metal is pushed out from between the metal bumps of the main chip and the metal bumps of the sub-chips respectively and flow sideways. Thereby, adjacent metal bumps are electrically short-circuited in an extreme case.
Further, in the case of carrying out such bonding using a semiconductor wafer instead of a main chip according to the abovementioned method, a number of (e.g. thousands of) sub-chips are bonded onto the semiconductor wafer. Consequently, the wafer and the sub-chips are in the over-heated state to a high temperature for a long time till all of the sub-chips are bonded. Thereby, the characteristics of the main chips and the sub-chips are degraded.
Further, a semiconductor wafer has a number of (thousands of) regions each corresponding to a main chip, and therefore, it is impossible to press sub-chips against all of the regions each corresponding to a main chip at one time and heat them. Therefore, in the abovementioned second manufacturing method, it is necessary to transfer a sub-chip to a predetermined position above the semiconductor wafer by means of a vacuum collet, heat and cool the same with applying a load on the sub-chip and repeat these steps as many times as the number of the sub-chips. This results in a low productivity.
Further, at the time of bonding the main chip and the sub-chip together, the metal bumps of the main chip and the metal bumps of the sub-chip are required to be accurately positioned with respect each other. However, a device used for bonding gets out of order because of its heat history accompanied by heating and cooling, so that the accuracy of the positioning cannot be made high.
Furthermore, at the time of bonding the main chip and the sub-chip, for example, if the sub-chip are electrically charged, the functional elements on the main chip are electrostatically damaged by electric discharge from the sub-chip when the metal bumps of the main chip and the metal bumps of the sub-chip come into contact with each other. In order to prevent such damage from occurring, the main chip is provided with a protective diode connected to the metal bumps. However, such a protective diode in itself is unnecessary, and if such a protective diode is provided, the area used for forming other functional elements is reduced.
An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suitably bonding together metal bumps formed on a first semiconductor substrate and metal bumps formed on a second semiconductor substrate respectively.
Another object of the present invention is to provide a method for manufacturing a semiconductor device in which characteristics of the semiconductor substrates are hard to be degraded.
A further object of the present invention is to provide a method for manufacturing a semiconductor device having a high productivity.
A further object of the present invention is to provide a method for manufacturing a semiconductor device capable of bonding a plurality of semiconductor substrates with reducing unalignment or displacement thereof.
A further object of the present invention is to provide a method for manufacturing a semiconductor device in which it is unnecessary to provide a protective diode on a semiconductor substrate for preventing electrostatic damage from occurring at the time of bonding a plurality of semiconductor substrates.
A method for manufacturing a semiconductor device according to a first aspect of the present invention is a method for manufacturing a semiconductor device by bonding a first metal bump formed on a first semiconductor substrate and a second metal bump formed on a second semiconductor substrate. This method includes a low melting point metal layer forming step for forming a low melting point metal layer on a top portion of at least either of the first metal bump and the second metal bump, a substrate temperature controlling step for, with the first semiconductor substrate and the second semiconductor substrate being separated from each other, controlling the temperature of the first semiconductor substrate to a first temperature higher than a solidus temperature of the low melting point metal and controlling the temperature of the second semiconductor substrate to a second temperature lower than a solidus temperature of the low melting point metal, a metal bump approaching step for bringing the first metal bump and the second metal bump close to each other after the substrate temperature controlling step, and a step for controlling, after the metal bump approaching step, the temperatures of the first semiconductor substrate and the second semiconductor substrate to a temperature lower than the solidus temperature of the low melting point metal.
According to the present invention, for example, in a case that a low melting point metal layer is formed on the first metal bump, a melt of the low melting point metal is produced at the substrate temperature controlling step. On the other hand, at the substrate temperature controlling step, the temperature of the second metal bump is controlled to be lower than the solidus temperature of the low melting point metal. At the metal bump approaching step, the low melting point metal layer comes into contact with the second metal bump, the melt of the low melting point metal is cooled and solidifies. When cooled, the melt of the low melting point metal is hard to flow if it does not completely solidify.
Therefore, the melt of the low melting point metal does not flow from between the first metal bump and the second metal bump.
Thereafter, by the step of controlling the temperatures of the first semiconductor substrate and the second semiconductor substrate to a temperature lower than the solidus temperature of the low melting point metal, the melt of the low melting point metal solidifies, so that the first metal bump and the second metal bump are electrically and mechanically bonded through the low melting point metal.
Similar is the case in which low melting point metal layers are formed respectively on the top portions of both of the first metal bump and the second metal bump.
The form of the semiconductor substrate can be, for example, a semiconductor chip (main chip, sub-chip) or a semiconductor wafer from which semiconductor chips are to be cut out. The metal bump can be formed of gold (Au), and the low melting point metal layer can be formed of, for example, a solder of tin, a tin-lead alloy, a tin-silver-copper alloy, or indium. The second temperature may be room temperature.
The abovementioned advantages can be more easily obtained when the difference between the first temperature and the second temperature is somewhat large. Therefore, the difference between the first temperature and the second temperature can be, for example, 100xc2x0 C. or more. Further, the difference between the first temperature and the second temperature may be 200xc2x0 C. or more.
The abovementioned substrate temperature controlling step may includes an oppositely disposing step for disposing the first semiconductor substrate and the second semiconductor substrate substantially horizontally and in a vertically opposed state.
By the oppositely disposing step, the first semiconductor substrate and the second semiconductor substrate are disposed substantially horizontal and vertically opposed to each other. At the metal bump approaching step, the first semiconductor substrate and the second semiconductor substrate can be brought to be close to each other with keeping this state. In this case, the melt of the low melting point metal is sandwiched between the first metal bump and the second metal bump in the vertical direction. Therefore, the melt of the low melting point metal is hard to flow out from between the first metal bump and the second metal bump.
The low melting point metal layers are formed on the top portion of the second metal bump, and therefore it is not always necessary to form the low melting point metal layers on the top portion of the first metal bump respectively.
With such a structure, at the substrate temperature controlling step, the temperature of the second semiconductor substrate is lower than the solidus temperature of the low melting point metal, and therefore the low melting point metal layer does not melt. On the other hand, at the substrate temperature controlling step, the temperature of the first metal bumps is made to be higher than the solidus temperature of the low melting point metal. And when the first metal bump comes into contact with the low melting point metal layer formed on the second metal bump by the metal bump approaching step, a portion of low melting point metal layer adjacent to the contact portion is heated by the first metal bump to a temperature higher than the solidus temperature of the low melting point metal, and thereby a melt of the low melting point metal is produced.
Thereafter, by the step of cooling the first semiconductor substrate and the second semiconductor substrate to a temperature lower than the solidus temperature of the low melting point metal, the melt of the low melting point metal solidifies, so that the first metal bump and the second metal bump are electrically and mechanically bonded together through the low melting point metal layer.
At this time, by the metal bump approaching step, low melting point metal layer formed on the second metal bump melts only in its contact portion with the first metal bump and its portion adjacent thereto. Therefore, the melt of the low melting point metal is prevented from flowing from between the first metal bump and the second metal bump. In such a manner, the first metal bump and the second metal bump can be suitably bonded. It is preferable that the area of the first metal bump is smaller than that of the second metal bump when seen in the direction perpendicular to the first and second semiconductor substrates and the first metal bump and the second metal bump are bonded with the first metal bump being completely superposed on the second metal bump. In this case, the contact portion of the first metal bump with the low melting point metal layer becomes small with respect to the whole area of the low melting point metal layer, and the abovementioned advantages can be remarkably obtained.
The first semiconductor substrate may be a semiconductor chip, and in this case, the second semiconductor substrate may be a semiconductor wafer.
The semiconductor wafer can include a number of (e.g. thousands of) regions each corresponding to a semiconductor chip.
With this arrangement, the semiconductor chips can be bonded onto the wafer. At the substrate temperature controlling step, the temperature of the semiconductor wafer as the second semiconductor substrate is controlled to the second temperature, namely, a low temperature lower than the melting point of the low melting point metal. Consequently, for example, if the semiconductor wafer is kept at the second temperature for a long time required for bonding thousands of semiconductor chips onto the semiconductor wafer, the characteristics of the semiconductor wafer are hard to be degraded.
After all of the semiconductor chips are bonded onto the semiconductor wafer, the semiconductor chips can be cut out from the semiconductor wafer. Thereby, the first and the second semiconductor chips each having a Chip-On-Chip structure can be obtained. In such a method for manufacturing a semiconductor device, bonding of the semiconductor chips is carried out with one semiconductor chip being at level of a semiconductor wafer, so that a high productivity can be obtained.
A method for manufacturing a semiconductor device according to a second aspect of the present invention is a method for manufacturing a semiconductor device having a structure in which a first metal bump formed on a surface of a first semiconductor substrate and a second metal bump formed on a surface of second semiconductor substrate are bonded together. This method includes a step of forming a layer of a low melting point metal on a top portion of at least either of the first metal bump and the second metal bump, a flux applying step for applying flux on the top portion of at least either of the first metal bump and the second metal bump, a temporarily fixing step for opposing, after the flux applying step, the surface of the first semiconductor substrate and the surface of the second semiconductor substrate to each other and temporarily fixing the first metal bump and the second metal bump to each other through the flux to each other, and a heating step for heating, after the temporarily fixing step, the first semiconductor substrate and the second semiconductor substrate to a temperature higher than the solidus temperature of the low melting point metal.
According to the present invention, the first metal bump and the second metal bump are bonded through the flux as an insulator. Therefore, if one of the first and second semiconductor substrates is electrically charged, no electrical discharge occurs at the time of this temporarily fixing, and so the functional elements provided on the other semiconductor substrate are not electrostatically damaged. Consequently, the first and the second semiconductor substrates need not be provided with any protective diode for preventing electrostatic damage from occurring at the time of bonding.
After temporarily fixing the first metal bump and the second metal bump, the first and the second semiconductor substrates are heated to a temperature higher than the solidus temperature of the low melting point metal, so that a melt of the low melting point metal is produced.
Then, by cooling the first and the second semiconductor substrates to a temperature lower than the solidus temperature of the low melting point metal, the first metal bump and the second metal bump are electrically and mechanically bonded together through the low melting point metal layer. At this time, if oxide films are formed on the surfaces of the first and the second metal bumps, the oxide films are removed by the action of the flux and the melt of the low melting point metal has a high wettability with respect to the first and the second metal bumps. Consequently, the first metal bump and the second metal bump can be suitably bonded together through the low melting point metal layer.
The first and the second metal bumps may be formed of, for example, gold (Au), and the low melting point metal layer may be formed of, for example, tin (Sn).
The abovementiond heating step may be carried out in a substantially unloaded state in which no load for pressing the first and the second semiconductor substrates against each other is applied on the first or second semiconductor substrates.
With this arrangement, the first and the second semiconductor substrates are heated in a substantially unloaded state in which, for example, one of the first and the second semiconductor substrates is horizontally placed and the other semiconductor substrate is mounted thereon. In this state, the upper semiconductor substrate is pressed against the lower semiconductor substrate only by its own weight and the first and the second semiconductor substrates are not compulsorily pressed against each other by any outer load, so that they can move relative to each other. Therefore, if the first metal bump and the second metal bump are temporarily fixed in the state of somewhat out of alignment or with some displacement by the temporarily fixing step, the first metal bump and the second metal bump move (self-align) so as to reduce such a displacement due to the surface tension of the melt of the low melting point metal when the melt is produced by the heating step. Therefore, the first metal bump and the second metal bump can be bonded together with a reduced displacement.
Further, since a step of applying a load on the first and the second semiconductor substrates can be omitted, a high productivity can be obtained.
The temporarily fixing step may include a step of temporarily fixing a plurality of first semiconductor substrates onto the surface of the second semiconductor substrate.
With this arrangement, after the plurality of first semiconductor substrates are temporarily fixed onto the surface of the second semiconductor substrate, the first and the second semiconductor substrates can be heated as a lump. That is, it is not necessary to repeat heating and cooling as many times as the number of the sub-chips. Consequently, the second semiconductor substrate and the plurality of first semiconductor substrates are bonded as a lump, so that a high productivity can be obtained.
The first semiconductor substrate may be, for example, a semiconductor chip and the second semiconductor substrate may be, for example, a semiconductor wafer. In this case, after the first and the second semiconductor substrates are bonded together, the second semiconductor substrate can be cut into pieces of semiconductor chips each having a Chip-On-Chip structure.
The abovementioned and other objects, features and advantages of the present invention will become more apparent from the following explanation given with reference to the appended drawings.